10-bit Charge redistributed D/A converter for TFT-LCD driver

Juneseok Lee, Doobock Lee, Hyosang Kim, Junho Moon, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, a 10-bit charge redistributed CMOS D/A Converter is presented for LCD panel driving. The structure of the charge redistributed D/A Converter is consisted of OP-AMP as Unit Gain Sampler, two parallel capacitors, a CMOS switch, and a digital block. In order to solve the capacitor mismatching problem, a compensation method to use alternate capacitors is proposed. Further, the D/A Converter has a digital block to change the digital parallel data into the serial data,which is based on JCCG (Johnson Counter Clock Generator).The chip was fabricated with a 0.35μm 1-poly 4-metal n-well CMOS technology. The effective chip area is 430μm×880μm and it dissipates about 0.607mW power consumption at 3.3V power supply. The INL and DNL is within ±0.41 LSB and ±0.11 LSB,respectively.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
PagesIII3-III4
DOIs
StatePublished - 2008
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 24 Nov 200825 Nov 2008

Publication series

Name2008 International SoC Design Conference, ISOCC 2008
Volume3

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
Country/TerritoryKorea, Republic of
CityBusan
Period24/11/0825/11/08

Keywords

  • A charge redistribution D/A Converter
  • CMOS switch
  • JCCG
  • Two parallel capacitor

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