12-bit 80MSPS double folding/interpolation A/D converter

Byungil Kim, Daeyun Kim, Jooho Hwang, Junho Moon, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18um 1-poly 6-metal CMOS technology. The active area is 1.6mm2 and 195mw at 1.8V power supply. The DNL and INL are within ±4/ ±4LSB, respectively. The measured result of SNDR is 46dB,when Fin=1MHz at s=80MHz.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
PagesIII1-III2
DOIs
StatePublished - 2008
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 24 Nov 200825 Nov 2008

Publication series

Name2008 International SoC Design Conference, ISOCC 2008
Volume3

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
Country/TerritoryKorea, Republic of
CityBusan
Period24/11/0825/11/08

Keywords

  • ADC
  • Folding
  • Interpolating

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