3 V 6-Bit 70 MSPS dual CMOS A/D converter for DBS (Direct Broadcasting for Satellite)

  • Ho Young Lee
  • , Jae Jin Park
  • , Min Kyu Song
  • , Jae Whui Kim
  • , Kwong Hyun Kim

Research output: Contribution to journalConference articlepeer-review

Abstract

In a front-end receiver of DBS (Direct Broadcasting for Satellite), an A/D converter, which converts I/Q signals of QPSK demodulator into digital domain, makes an important role to determine the system performance. In this paper a 3 V dual A/D converter which has 6-b resolution and 70 MSPS conversion rate is proposed. It has the dual flash architecture in which comparators use auto-zero offset cancellation technique. With 0.65 um double-poly and double-metal CMOS technology, the experimental prototype of the proposed A/D converter has ±0.7 LSB INL and ±0.9 LSB DNL.

Original languageEnglish
Pages (from-to)422-423
Number of pages2
JournalDigest of Technical Papers - IEEE International Conference on Consumer Electronics
StatePublished - 1997
EventProceedings of the 1997 16th International Conference on Consumer Electronics, ICCE - Rosemont, IL, USA
Duration: 11 Jun 199713 Jun 1997

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