A 10-b 500 MS/s CMOS folding A/D converter with a hybrid calibration and a novel digital error correction logic

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ±0.8 LSB and an INL of ±1.0 LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is 1.55 mm², and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply. Index Terms-Analog digital converter, folding, interpolation, digital correction logic, calibration.