TY - JOUR
T1 - A 12-bit 100 MSPS Full-Swing Current-Steering Digital-to-Analog Converter with Half-Power Supply Calibration Technique
AU - Park, Kwangjin
AU - Choi, Seung Gu
AU - Kim, Jintae
AU - Kim, Myungsik
AU - Song, Hyunjin
AU - Song, Minkyu
AU - Kim, Soo Youn
N1 - Publisher Copyright:
© 2025 by the authors.
PY - 2025/10
Y1 - 2025/10
N2 - We present a digital-to-analog converter (DAC) with full-swing DAC output and a proposed half-power supply calibration technique. To generate a full-swing DAC output, symmetric thermometer decoders and an output selector are implemented to select the appropriate current cell according to the output voltage range. Furthermore, to improve the linearity, we propose a half-power supply calibration circuit consisting of comparators and calibration counters to control the current of the current cells at the half-power supply voltage point, where the voltage mismatch typically occurs. The DAC was fabricated in a 28 nm CMOS process, with a full chip area of 0.95 mm × 0.93 mm. The measurement results demonstrate a maximum voltage mismatch improvement of 95% when using the proposed half-power supply calibration technique, with DNL and INL values of 0.39 and 1.15 LSB. The total power consumption was 73.8 mW at 100 MSPS, with analog and digital supply voltages of 1.8 and 1.0 V, respectively.
AB - We present a digital-to-analog converter (DAC) with full-swing DAC output and a proposed half-power supply calibration technique. To generate a full-swing DAC output, symmetric thermometer decoders and an output selector are implemented to select the appropriate current cell according to the output voltage range. Furthermore, to improve the linearity, we propose a half-power supply calibration circuit consisting of comparators and calibration counters to control the current of the current cells at the half-power supply voltage point, where the voltage mismatch typically occurs. The DAC was fabricated in a 28 nm CMOS process, with a full chip area of 0.95 mm × 0.93 mm. The measurement results demonstrate a maximum voltage mismatch improvement of 95% when using the proposed half-power supply calibration technique, with DNL and INL values of 0.39 and 1.15 LSB. The total power consumption was 73.8 mW at 100 MSPS, with analog and digital supply voltages of 1.8 and 1.0 V, respectively.
KW - differential non-linearity
KW - digital-to-analog converter
KW - foreground calibration
KW - full-swing DAC
UR - https://www.scopus.com/pages/publications/105019041304
U2 - 10.3390/electronics14193955
DO - 10.3390/electronics14193955
M3 - Article
AN - SCOPUS:105019041304
SN - 2079-9292
VL - 14
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 19
M1 - 3955
ER -