@inproceedings{8ed4ab4dda06427486f9c99c5325fbbc,
title = "A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation",
abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm 2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs/2 at F s=1GHz.",
keywords = "ADC, Auto-switching encoder, Cascaded-folding, Folder averaging",
author = "Jooho Hwang and Dongheon Lee and Sunghyun Park and Junho Moon and Minkyu Song",
year = "2009",
doi = "10.1109/ICICDT.2009.5166304",
language = "English",
isbn = "9781424429332",
series = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",
pages = "241--244",
booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",
note = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 ; Conference date: 18-05-2009 Through 20-05-2009",
}