A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation

Jooho Hwang, Dongheon Lee, Sunghyun Park, Junho Moon, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm 2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs/2 at F s=1GHz.

Original languageEnglish
Title of host publication2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages241-244
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States
Duration: 18 May 200920 May 2009

Publication series

Name2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Country/TerritoryUnited States
CityAustin, TX
Period18/05/0920/05/09

Keywords

  • ADC
  • Auto-switching encoder
  • Cascaded-folding
  • Folder averaging

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