A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation

Jooho Hwang; Dongheon Lee; Sunghyun Park; Junho Moon; Minkyu Song

doi:10.1109/ICICDT.2009.5166304

A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation

Jooho Hwang
, Dongheon Lee
, Sunghyun Park
, Junho Moon
, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm ² and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when F_in= F_s/2 at F _s=1GHz.

Original language	English
Title of host publication	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Pages	241-244
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2009.5166304
State	Published - 2009
Event	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 - Austin, TX, United States Duration: 18 May 2009 → 20 May 2009

Publication series

Name	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009

Conference

Conference	2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009
Country/Territory	United States
City	Austin, TX
Period	18/05/09 → 20/05/09

Keywords

ADC
Auto-switching encoder
Cascaded-folding
Folder averaging

Access to Document

10.1109/ICICDT.2009.5166304

Cite this

Hwang, J., Lee, D., Park, S., Moon, J., & Song, M. (2009). A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 (pp. 241-244). Article 5166304 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). https://doi.org/10.1109/ICICDT.2009.5166304

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title = "A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation",

abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm 2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs/2 at F s=1GHz.",

keywords = "ADC, Auto-switching encoder, Cascaded-folding, Folder averaging",

author = "Jooho Hwang and Dongheon Lee and Sunghyun Park and Junho Moon and Minkyu Song",

year = "2009",

doi = "10.1109/ICICDT.2009.5166304",

language = "English",

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series = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

pages = "241--244",

booktitle = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009",

note = "2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009 ; Conference date: 18-05-2009 Through 20-05-2009",

}

Hwang, J, Lee, D, Park, S, Moon, J & Song, M 2009, A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation. in 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009., 5166304, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, pp. 241-244, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009, Austin, TX, United States, 18/05/09. https://doi.org/10.1109/ICICDT.2009.5166304

A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation. / Hwang, Jooho; Lee, Dongheon; Park, Sunghyun et al.
2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 241-244 5166304 (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Moon, Junho

AU - Song, Minkyu

PY - 2009

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N2 - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm 2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs/2 at F s=1GHz.

AB - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm 2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs/2 at F s=1GHz.

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Hwang J, Lee D, Park S, Moon J, Song M. A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation. In 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. 2009. p. 241-244. 5166304. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009). doi: 10.1109/ICICDT.2009.5166304

A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation

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Keywords

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