A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder

Junho Moon, Heewon Kang, Daeyoon Kim, Seungjin Yeo, Dubok Lee, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit IGS/s at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of IGS/s, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW, of power. The measured INL and DNL were within ± 0.5LSB, ± 0.7LSB, respectively. The measured SNDR, was 33.82dB, when the An=100MHz at Fs=500MHz. The active chip occupies an area of 0.27mm2 in 0.18μm CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages638-641
Number of pages4
DOIs
StatePublished - 2008
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: 31 Aug 20083 Sep 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Country/TerritoryMalta
CitySt. Julian's
Period31/08/083/09/08

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