Abstract
In a front-end receiver of DBS (Direct Broadcasting for Satellite), an A/D converter, which converts I/Q signals of QPSK demodulator into digital domain, makes an important role to determine the system performance. In this paper a 3 V dual A/D converter which has 6-b resolution and 70 MSPS conversion rate is proposed. It has the dual flash architecture in which comparators use auto-zero offset cancellation technique. With 0.65 um double-poly and double-metal CMOS technology, the experimental prototype of the proposed A/D converter has ±0.7 LSB INL and ±0.9 LSB DNL.
Original language | English |
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Pages (from-to) | 863-867 |
Number of pages | 5 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 43 |
Issue number | 3 |
DOIs | |
State | Published - 1997 |