Abstract
In this paper, a 3V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributing track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 μm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 μm × 800 μm and it dissipates about 210 mW at 3V power supply. The INL is within ±1 LSB and DNL is within ±1 LSB, respectively. The SNR is about 43 dB, when the input frequency is 10 MHz at 200 MHz clock frequency.
Original language | English |
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Pages (from-to) | 1554-1561 |
Number of pages | 8 |
Journal | IEICE Transactions on Electronics |
Volume | E85-C |
Issue number | 8 |
State | Published - Aug 2002 |
Keywords
- A delay error correction
- A digital encoder
- A folding/interpolation ADC
- An analog latch