A 45 nm 9-bit 1 GS/s high precision CMOS folding A/D converter with an odd number of folding blocks

Seongjoo Lee, Jangwoo Lee, Minkyu Song

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

In this paper, a 9-bit 1GS/s high precision folding A/D converter with a 45 nm CMOS technology is proposed. In order to improve the asymmetrical boundary condition error of a conventional folding ADC, a novel scheme with an odd number of folding blocks is proposed. Further, a new digital encoding technique is described to implement the odd number of folding technique. The proposed ADC employs a digital error correction circuit to minimize device mismatch and external noise. The chip has been fabricated with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99 mm2 and the power dissipation is about 120 mW. The measured result of SNDR is 45.35 dB, when the input frequency is 150 MHz at the sampling frequency of 1 GHz. The measured INL is within +7 LSB/-3 LSB and DNL is within +1.5 LSB/-1 LSB.

Original languageEnglish
Pages (from-to)376-382
Number of pages7
JournalJournal of Semiconductor Technology and Science
Volume14
Issue number4
DOIs
StatePublished - 2014

Keywords

  • DNL
  • Folding ADC
  • High precision ADC
  • INL
  • Odd number of folding blocks
  • SNDR

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