A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

Yujin Park; Sanghoon Hwang; Minkyu Song

doi:10.1109/NEWCAS.2005.1496704

A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

Yujin Park, Sanghoon Hwang, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed Track-and-Hold (T/H), a novel One-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18um CMOS occupies an area of 977um × 1040um and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.

Original language	English
Title of host publication	3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Pages	51-54
Number of pages	4
DOIs	https://doi.org/10.1109/NEWCAS.2005.1496704
State	Published - 2005
Event	3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005 - Quebec City, QC, Canada Duration: 19 Jun 2005 → 22 Jun 2005

Publication series

Name	3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Volume	2005

Conference

Conference	3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005
Country/Territory	Canada
City	Quebec City, QC
Period	19/06/05 → 22/06/05

Access to Document

10.1109/NEWCAS.2005.1496704

Cite this

Park, Y., Hwang, S., & Song, M. (2005). A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder. In 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005 (pp. 51-54). Article 1496704 (3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005; Vol. 2005). https://doi.org/10.1109/NEWCAS.2005.1496704

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title = "A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder",

abstract = "In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed Track-and-Hold (T/H), a novel One-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18um CMOS occupies an area of 977um × 1040um and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.",

author = "Yujin Park and Sanghoon Hwang and Minkyu Song",

year = "2005",

doi = "10.1109/NEWCAS.2005.1496704",

language = "English",

isbn = "0780389344",

series = "3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005",

pages = "51--54",

booktitle = "3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005",

note = "3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005 ; Conference date: 19-06-2005 Through 22-06-2005",

}

Park, Y, Hwang, S & Song, M 2005, A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder. in 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005., 1496704, 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005, vol. 2005, pp. 51-54, 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005, Quebec City, QC, Canada, 19/06/05. https://doi.org/10.1109/NEWCAS.2005.1496704

A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder. / Park, Yujin; Hwang, Sanghoon; Song, Minkyu.
3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005. 2005. p. 51-54 1496704 (3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed Track-and-Hold (T/H), a novel One-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18um CMOS occupies an area of 977um × 1040um and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.

AB - In this paper, CMOS analog-to-digital converter (ADC) with a 6bits 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a high speed Track-and-Hold (T/H), a novel One-zero detecting encoder, and a buffered reference for the improvement of SNR are proposed. The fabricated chip with 0.18um CMOS occupies an area of 977um × 1040um and consumes 145mW at 1.8V power supply. The measured SNDR is about 34.55dB and DNL is within 0.5LSB, when the sampling frequency is 2GHz.

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Park Y, Hwang S, Song M. A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder. In 3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005. 2005. p. 51-54. 1496704. (3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005). doi: 10.1109/NEWCAS.2005.1496704

A 6-bit 2GSPS interpolated flash type CMOS A/D converter with a buffered DC reference and one-zero detecting encoder

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