A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique

Moon Junho; Jung Seunghwi; Hwang Sanghoon; Song Minkyu

doi:10.1109/ICECS.2006.379739

A 6b 100MS/s 0.28mm² 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique

Moon Junho, Jung Seunghwi, Hwang Sanghoon, Song Minkyu

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm² in 0.18um CMOS technology.

Original language	English
Title of host publication	ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages	140-143
Number of pages	4
DOIs	https://doi.org/10.1109/ICECS.2006.379739
State	Published - 2006
Event	ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France Duration: 10 Dec 2006 → 13 Dec 2006

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference	ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Country/Territory	France
City	Nice
Period	10/12/06 → 13/12/06

Access to Document

10.1109/ICECS.2006.379739

Cite this

Junho, M., Seunghwi, J., Sanghoon, H., & Minkyu, S. (2006). A 6b 100MS/s 0.28mm² 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique. In ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems (pp. 140-143). Article 4263323 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). https://doi.org/10.1109/ICECS.2006.379739

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title = "A 6b 100MS/s 0.28mm2 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique",

abstract = "In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18um CMOS technology.",

author = "Moon Junho and Jung Seunghwi and Hwang Sanghoon and Song Minkyu",

year = "2006",

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series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

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note = "ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems ; Conference date: 10-12-2006 Through 13-12-2006",

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Junho, M, Seunghwi, J, Sanghoon, H & Minkyu, S 2006, A 6b 100MS/s 0.28mm² 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique. in ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems., 4263323, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 140-143, ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France, 10/12/06. https://doi.org/10.1109/ICECS.2006.379739

A 6b 100MS/s 0.28mm² 5mW 0.18um CMOS F/I ADC with a novel folder reduction technique. / Junho, Moon; Seunghwi, Jung; Sanghoon, Hwang et al.
ICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems. 2006. p. 140-143 4263323 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18um CMOS technology.

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