TY - JOUR
T1 - A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system
AU - Lee, Seongjoo
AU - Song, Minkyu
PY - 2013/7
Y1 - 2013/7
N2 - In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.
AB - In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.
KW - Battery management system (BMS)
KW - Cyclic folding A/D converter (ADC)
KW - Folding-interpolation architecture
UR - http://www.scopus.com/inward/record.url?scp=84879831200&partnerID=8YFLogxK
U2 - 10.1007/s10470-013-0080-4
DO - 10.1007/s10470-013-0080-4
M3 - Article
AN - SCOPUS:84879831200
SN - 0925-1030
VL - 76
SP - 15
EP - 21
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
IS - 1
ER -