A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.