Abstract
This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10-11 BER.
Original language | English |
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Article number | 5342367 |
Pages (from-to) | 3434-3447 |
Number of pages | 14 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 44 |
Issue number | 12 |
DOIs | |
State | Published - Dec 2009 |
Keywords
- 60 GHz
- CMOS
- Decision feedback equalizer
- Direct-conversion transceiver
- Low-noise amplifier (LNA)
- Millimeter-wave integrated circuits
- Mixer
- Phase-locked loop (PLL)
- Power amplifier
- Voltage-controlled oscillator (VCO)