A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry

Cristian Marcu; Debopriyo Chowdhury; Chintan Thakkar; Jung Dong Park; Ling Kai Kong; Maryam Tabesh; Yanjie Wang; Bagher Afshar; Abhinav Gupta; Amin Arbabian; Simone Gambini; Reza Zamani; Elad Alon; Ali M. Niknejad

doi:10.1109/JSSC.2009.2032584

A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry

Cristian Marcu
, Debopriyo Chowdhury
, Chintan Thakkar
, Jung Dong Park
, Ling Kai Kong
, Maryam Tabesh
, Yanjie Wang
, Bagher Afshar
, Abhinav Gupta
, Amin Arbabian
, Simone Gambini
, Reza Zamani
, Elad Alon
, Ali M. Niknejad

Department of Electronics & Electrical Engineering

Research output: Contribution to journal › Article › peer-review

220 Scopus citations

Abstract

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10^-11 BER.

Original language	English
Article number	5342367
Pages (from-to)	3434-3447
Number of pages	14
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	12
DOIs	https://doi.org/10.1109/JSSC.2009.2032584
State	Published - Dec 2009

Keywords

60 GHz
CMOS
Decision feedback equalizer
Direct-conversion transceiver
Low-noise amplifier (LNA)
Millimeter-wave integrated circuits
Mixer
Phase-locked loop (PLL)
Power amplifier
Voltage-controlled oscillator (VCO)

Access to Document

10.1109/JSSC.2009.2032584

Cite this

Marcu, C., Chowdhury, D., Thakkar, C., Park, J. D., Kong, L. K., Tabesh, M., Wang, Y., Afshar, B., Gupta, A., Arbabian, A., Gambini, S., Zamani, R., Alon, E., & Niknejad, A. M. (2009). A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry. IEEE Journal of Solid-State Circuits, 44(12), 3434-3447. Article 5342367. https://doi.org/10.1109/JSSC.2009.2032584

@article{14d61978ec374314aee22f355cdca924,

title = "A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry",

abstract = "This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10-11 BER.",

keywords = "60 GHz, CMOS, Decision feedback equalizer, Direct-conversion transceiver, Low-noise amplifier (LNA), Millimeter-wave integrated circuits, Mixer, Phase-locked loop (PLL), Power amplifier, Voltage-controlled oscillator (VCO)",

author = "Cristian Marcu and Debopriyo Chowdhury and Chintan Thakkar and Park, \{Jung Dong\} and Kong, \{Ling Kai\} and Maryam Tabesh and Yanjie Wang and Bagher Afshar and Abhinav Gupta and Amin Arbabian and Simone Gambini and Reza Zamani and Elad Alon and Niknejad, \{Ali M.\}",

year = "2009",

month = dec,

doi = "10.1109/JSSC.2009.2032584",

language = "English",

volume = "44",

pages = "3434--3447",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

TY - JOUR

T1 - A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry

AU - Marcu, Cristian

AU - Chowdhury, Debopriyo

AU - Thakkar, Chintan

AU - Park, Jung Dong

AU - Kong, Ling Kai

AU - Tabesh, Maryam

AU - Wang, Yanjie

AU - Afshar, Bagher

AU - Gupta, Abhinav

AU - Arbabian, Amin

AU - Gambini, Simone

AU - Zamani, Reza

AU - Alon, Elad

AU - Niknejad, Ali M.

PY - 2009/12

Y1 - 2009/12

N2 - This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

AB - This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

KW - 60 GHz

KW - CMOS

KW - Decision feedback equalizer

KW - Direct-conversion transceiver

KW - Low-noise amplifier (LNA)

KW - Millimeter-wave integrated circuits

KW - Mixer

KW - Phase-locked loop (PLL)

KW - Power amplifier

KW - Voltage-controlled oscillator (VCO)

UR - https://www.scopus.com/pages/publications/72949089983

U2 - 10.1109/JSSC.2009.2032584

DO - 10.1109/JSSC.2009.2032584

M3 - Article

AN - SCOPUS:72949089983

SN - 0018-9200

VL - 44

SP - 3434

EP - 3447

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 12

M1 - 5342367

ER -

A 90 nm CMOS low-power 60 GHz transceiver with integrated baseband circuitry

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this