Abstract
A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, we fabricated a test pattern using a 1.2-μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also enables a decrease in area of about 20%.
Original language | English |
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Pages (from-to) | 133-137 |
Number of pages | 5 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 28 |
Issue number | 2 |
DOIs | |
State | Published - Feb 1993 |