A Clock Feedthrough Reduction Circuit for Switched-Current Systems

A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, we fabricated a test pattern using a 1.2-μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also enables a decrease in area of about 20%.