TY - GEN
T1 - A CMOS cyclic folding A/D converter with a new compact layout technique
AU - Lee, Seongjoo
AU - Park, Dowoo
AU - Bae, Jaeyoung
AU - Song, Minkyu
PY - 2013
Y1 - 2013
N2 - In this paper, a 9-bit 2MS/s CMOS cyclic folding A/D Converter(ADC) for a Battery Management System(BMS) is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 1mW at 3.3V. The occupied active die area is 10mm2.
AB - In this paper, a 9-bit 2MS/s CMOS cyclic folding A/D Converter(ADC) for a Battery Management System(BMS) is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 1mW at 3.3V. The occupied active die area is 10mm2.
UR - https://www.scopus.com/pages/publications/84883484801
U2 - 10.1109/NEWCAS.2013.6573571
DO - 10.1109/NEWCAS.2013.6573571
M3 - Conference contribution
AN - SCOPUS:84883484801
SN - 9781479906185
T3 - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
BT - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
T2 - 2013 IEEE 11th International New Circuits and Systems Conference, NEWCAS 2013
Y2 - 16 June 2013 through 19 June 2013
ER -