A digitally self-calibrated low-noise 7-bit folding A/D converter

Minah Kwon; Dahsom Kim; Daeyun Kim; Junho Moon; Minkyu Song

doi:10.1109/SOCC.2010.5784637

A digitally self-calibrated low-noise 7-bit folding A/D converter

Minah Kwon, Dahsom Kim, Daeyun Kim, Junho Moon, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2010
Pages	39-43
Number of pages	5
DOIs	https://doi.org/10.1109/SOCC.2010.5784637
State	Published - 2010
Event	23rd IEEE International SOC Conference, SOCC 2010 - Las Vegas, NV, United States Duration: 27 Sep 2010 → 29 Sep 2010

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2010

Conference

Conference	23rd IEEE International SOC Conference, SOCC 2010
Country/Territory	United States
City	Las Vegas, NV
Period	27/09/10 → 29/09/10

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10.1109/SOCC.2010.5784637

Cite this

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title = "A digitally self-calibrated low-noise 7-bit folding A/D converter",

abstract = "In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.",

author = "Minah Kwon and Dahsom Kim and Daeyun Kim and Junho Moon and Minkyu Song",

year = "2010",

doi = "10.1109/SOCC.2010.5784637",

language = "English",

isbn = "9781424466832",

series = "Proceedings - IEEE International SOC Conference, SOCC 2010",

pages = "39--43",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2010",

note = "23rd IEEE International SOC Conference, SOCC 2010 ; Conference date: 27-09-2010 Through 29-09-2010",

}

Kwon, M, Kim, D, Kim, D, Moon, J & Song, M 2010, A digitally self-calibrated low-noise 7-bit folding A/D converter. in Proceedings - IEEE International SOC Conference, SOCC 2010., 5784637, Proceedings - IEEE International SOC Conference, SOCC 2010, pp. 39-43, 23rd IEEE International SOC Conference, SOCC 2010, Las Vegas, NV, United States, 27/09/10. https://doi.org/10.1109/SOCC.2010.5784637

TY - GEN

T1 - A digitally self-calibrated low-noise 7-bit folding A/D converter

AU - Kwon, Minah

AU - Kim, Dahsom

AU - Kim, Daeyun

AU - Moon, Junho

AU - Song, Minkyu

PY - 2010

Y1 - 2010

N2 - In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

AB - In this paper, a low noise 65nm 1.2V 7-bit 1GSPS A/D converter with a digitally self-calibrated technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2 and its interpolation rate is 8. A digitally self-calibrated technique with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about 110mW with a 1.2V power supply. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

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U2 - 10.1109/SOCC.2010.5784637

DO - 10.1109/SOCC.2010.5784637

M3 - Conference contribution

AN - SCOPUS:79960715082

SN - 9781424466832

T3 - Proceedings - IEEE International SOC Conference, SOCC 2010

SP - 39

EP - 43

BT - Proceedings - IEEE International SOC Conference, SOCC 2010

T2 - 23rd IEEE International SOC Conference, SOCC 2010

Y2 - 27 September 2010 through 29 September 2010

ER -

A digitally self-calibrated low-noise 7-bit folding A/D converter

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