A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S.G. Conroy, Beomsup Kim

Research output: Contribution to journalArticlepeer-review

30 Scopus citations

Abstract

This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.

Original languageEnglish
Pages (from-to)462-470
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume40
Issue number2
DOIs
StatePublished - Feb 2005

Keywords

  • Adaptive equalizer
  • Clock data recovery (CDR)
  • Serial-link transceiver

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