A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

Jinwook Kim; Jeongsik Yang; Sangjin Byun; Hyunduk Jun; Jeongkyu Park; Cormac S.G. Conroy; Beomsup Kim

doi:10.1109/JSSC.2004.841037

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

Jinwook Kim
, Jeongsik Yang
, Sangjin Byun
, Hyunduk Jun
, Jeongkyu Park
, Cormac S.G. Conroy
, Beomsup Kim

Department of Electronics & Electrical Engineering

Research output: Contribution to journal › Article › peer-review

30 Scopus citations

Abstract

This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10^-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.

Original language	English
Pages (from-to)	462-470
Number of pages	9
Journal	IEEE Journal of Solid-State Circuits
Volume	40
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2004.841037
State	Published - Feb 2005

Keywords

Adaptive equalizer
Clock data recovery (CDR)
Serial-link transceiver

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10.1109/JSSC.2004.841037

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title = "A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer",

abstract = "This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.",

keywords = "Adaptive equalizer, Clock data recovery (CDR), Serial-link transceiver",

author = "Jinwook Kim and Jeongsik Yang and Sangjin Byun and Hyunduk Jun and Jeongkyu Park and Conroy, \{Cormac S.G.\} and Beomsup Kim",

year = "2005",

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doi = "10.1109/JSSC.2004.841037",

language = "English",

volume = "40",

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AU - Kim, Jinwook

AU - Yang, Jeongsik

AU - Byun, Sangjin

AU - Jun, Hyunduk

AU - Park, Jeongkyu

AU - Conroy, Cormac S.G.

AU - Kim, Beomsup

PY - 2005/2

Y1 - 2005/2

N2 - This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.

AB - This paper presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5 Gb/s for a single 10-Gbit extended Attachment Unit Interface (XAUI) in a standard 0.18-μm CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than < 4.5 × 10-15 while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.

KW - Adaptive equalizer

KW - Clock data recovery (CDR)

KW - Serial-link transceiver

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DO - 10.1109/JSSC.2004.841037

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SP - 462

EP - 470

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 2

ER -

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

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Keywords

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