A high dynamic range CMOS image sensor with a digital configurable logarithmic counter

Jaeyoung Bae, Daehyuk Kim, Inkyung Hwang, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Many kinds of high dynamic range (HDR) CMOS Image Sensors (CIS) have been reported, such as a multiple sampling, a multiple exposure technique, and so on. However, those techniques have some disadvantages of noise increasing, large power consumption, and huge chip area. In this paper, a new digital configurable logarithmic counter is described. Since the proposed scheme is easily implemented with a very simple technique, we can reduce power consumption and chip area drastically. Further, the logarithmic counter enhances the dynamic range (DR). The chip which has been fabricated using a 0.13um CIS process has an excellent SNDR at high speed sampling rate.

Original languageEnglish
Title of host publication2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings
PublisherIEEE Computer Society
ISBN (Print)9783000437854
DOIs
StatePublished - 2013
Event2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Dresden, Germany
Duration: 8 Sep 201312 Sep 2013

Publication series

Name2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings

Conference

Conference2013 European Conference on Circuit Theory and Design, ECCTD 2013
Country/TerritoryGermany
CityDresden
Period8/09/1312/09/13

Keywords

  • CMOS image sensor
  • configurable logarithmic counter
  • high dynamic range

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