TY - GEN
T1 - A high precision CMOS folding A/D Converter with an Odd number of folding blocks
AU - Park, Dowoo
AU - Lee, Seoungjoo
AU - Song, Minkyu
PY - 2013
Y1 - 2013
N2 - A high precision CMOS folding A/D Converter(ADC) with an odd number of folding blocks is described. In order to improve the performance of normal folding types with an even number of folding blocks, a new scheme is proposed. A novel digital encoder, a digital error correction logic, and a self-calibration technique are discussed. To verify the proposed technique, an 8-bit folding ADC is designed with a 0.13um CMOS process at 1.2V power supply. The measured values of INL and DNL are within 0.5LSB, respectively, and the measured SNDR is about 46dB at the conversion rate of 1GS/s.
AB - A high precision CMOS folding A/D Converter(ADC) with an odd number of folding blocks is described. In order to improve the performance of normal folding types with an even number of folding blocks, a new scheme is proposed. A novel digital encoder, a digital error correction logic, and a self-calibration technique are discussed. To verify the proposed technique, an 8-bit folding ADC is designed with a 0.13um CMOS process at 1.2V power supply. The measured values of INL and DNL are within 0.5LSB, respectively, and the measured SNDR is about 46dB at the conversion rate of 1GS/s.
KW - folding A/D converter
KW - odd number of folding blocks
KW - self-calibration technique
UR - http://www.scopus.com/inward/record.url?scp=84906908555&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2013.6863993
DO - 10.1109/ISOCC.2013.6863993
M3 - Conference contribution
AN - SCOPUS:84906908555
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 87
EP - 90
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -