A high precision CMOS folding A/D Converter with an Odd number of folding blocks

Dowoo Park, Seoungjoo Lee, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A high precision CMOS folding A/D Converter(ADC) with an odd number of folding blocks is described. In order to improve the performance of normal folding types with an even number of folding blocks, a new scheme is proposed. A novel digital encoder, a digital error correction logic, and a self-calibration technique are discussed. To verify the proposed technique, an 8-bit folding ADC is designed with a 0.13um CMOS process at 1.2V power supply. The measured values of INL and DNL are within 0.5LSB, respectively, and the measured SNDR is about 46dB at the conversion rate of 1GS/s.

Original languageEnglish
Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
PublisherIEEE Computer Society
Pages87-90
Number of pages4
ISBN (Print)9781479911417
DOIs
StatePublished - 2013
Event2013 International SoC Design Conference, ISOCC 2013 - Busan, Korea, Republic of
Duration: 17 Nov 201319 Nov 2013

Publication series

NameISOCC 2013 - 2013 International SoC Design Conference

Conference

Conference2013 International SoC Design Conference, ISOCC 2013
Country/TerritoryKorea, Republic of
CityBusan
Period17/11/1319/11/13

Keywords

  • folding A/D converter
  • odd number of folding blocks
  • self-calibration technique

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