A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique

Donggwi Choi, Dasom Kim, Kyuik Cho, Daeyun Kim, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about llOmW at 1.2V power supply. The measured SNDR is about 38.48dB when the input frequency is 250MHz at 1GHz sampling frequency. The measured SNDR is 3dB higher than the same ADC without any calibration.

Original languageEnglish
Title of host publication2010 International SoC Design Conference, ISOCC 2010
Pages194-197
Number of pages4
DOIs
StatePublished - 2010
Event2010 International SoC Design Conference, ISOCC 2010 - Incheon, Korea, Republic of
Duration: 22 Nov 201023 Nov 2010

Publication series

Name2010 International SoC Design Conference, ISOCC 2010

Conference

Conference2010 International SoC Design Conference, ISOCC 2010
Country/TerritoryKorea, Republic of
CityIncheon
Period22/11/1023/11/10

Keywords

  • A/D converter
  • Folding
  • Interpolation
  • Self-calibration

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