@inproceedings{f166814cfdb449389fcca4b7008cb172,
title = "A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique",
abstract = "In this paper, a 65nm 1.2V 7-bit 1GSPS A/D converter with a self-calibration technique is proposed. The A/D converter is based on a folding-interpolation structure whose folding rate is 2, interpolation rate is 8. An offset self-calibration circuit with a feedback loop and a recursive digital code inspection is described. The offset self-calibration circuit reduces the variation of the offset voltage, due to process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87mm2 and the power consumption is about llOmW at 1.2V power supply. The measured SNDR is about 38.48dB when the input frequency is 250MHz at 1GHz sampling frequency. The measured SNDR is 3dB higher than the same ADC without any calibration.",
keywords = "A/D converter, Folding, Interpolation, Self-calibration",
author = "Donggwi Choi and Dasom Kim and Kyuik Cho and Daeyun Kim and Minkyu Song",
year = "2010",
doi = "10.1109/SOCDC.2010.5682940",
language = "English",
isbn = "9781424486335",
series = "2010 International SoC Design Conference, ISOCC 2010",
pages = "194--197",
booktitle = "2010 International SoC Design Conference, ISOCC 2010",
note = "2010 International SoC Design Conference, ISOCC 2010 ; Conference date: 22-11-2010 Through 23-11-2010",
}