A low noisy triple channel graphic digitizer for UXGA compatible TFT LCD panels

S. Yoon; M. Song

doi:10.1109/ICCE.2001.935188

A low noisy triple channel graphic digitizer for UXGA compatible TFT LCD panels

S. Yoon
, M. Song

Division of System Semiconductor

Dongguk University

Research output: Contribution to journal › Conference article › peer-review

Abstract

A low noisy graphic digitizer is composed of an AGC, ADC, and PLL. In order to satisfy the specification of triple channel UXGA compatible TFT LCD panels, novel techniques and algorithms are proposed. It has been fabricated with a 5 metal 0.25um CMOS technology. The chip area is about 3.6 mm × 3.2 mm with 520mW power dissipation at 2.5V power supply. The maximum jitter noise of the PLL is about 10ps at 230MHz clock speed. The INL and DNL of the ADC are within 1LSB.

Original language	English
Pages (from-to)	4-5
Number of pages	2
Journal	Digest of Technical Papers - IEEE International Conference on Consumer Electronics
DOIs	https://doi.org/10.1109/ICCE.2001.935188
State	Published - 2001
Event	2001 Digest of Technical Papers -International Conference on Consumer Electronics - Los Angeles, CA, United States Duration: 19 Jun 2001 → 21 Jun 2001

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10.1109/ICCE.2001.935188

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abstract = "A low noisy graphic digitizer is composed of an AGC, ADC, and PLL. In order to satisfy the specification of triple channel UXGA compatible TFT LCD panels, novel techniques and algorithms are proposed. It has been fabricated with a 5 metal 0.25um CMOS technology. The chip area is about 3.6 mm × 3.2 mm with 520mW power dissipation at 2.5V power supply. The maximum jitter noise of the PLL is about 10ps at 230MHz clock speed. The INL and DNL of the ADC are within 1LSB.",

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AB - A low noisy graphic digitizer is composed of an AGC, ADC, and PLL. In order to satisfy the specification of triple channel UXGA compatible TFT LCD panels, novel techniques and algorithms are proposed. It has been fabricated with a 5 metal 0.25um CMOS technology. The chip area is about 3.6 mm × 3.2 mm with 520mW power dissipation at 2.5V power supply. The maximum jitter noise of the PLL is about 10ps at 230MHz clock speed. The INL and DNL of the ADC are within 1LSB.

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ER -

A low noisy triple channel graphic digitizer for UXGA compatible TFT LCD panels

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