TY - JOUR
T1 - A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique
AU - Lee, Seongjoo
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2014, Springer Science+Business Media New York.
PY - 2014/9/23
Y1 - 2014/9/23
N2 - A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.
AB - A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.
KW - Capacitor swapping technique
KW - Cyclic D/A converter (DAC)
KW - Improved Johnson counter
UR - http://www.scopus.com/inward/record.url?scp=84919401713&partnerID=8YFLogxK
U2 - 10.1007/s10470-014-0380-3
DO - 10.1007/s10470-014-0380-3
M3 - Article
AN - SCOPUS:84919401713
SN - 0925-1030
VL - 81
SP - 165
EP - 172
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
IS - 1
ER -