A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.