A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

Sekyoung Hong; Dalsoo Kim; Minkyu Song

doi:10.1109/30.883470

A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

Sekyoung Hong
, Dalsoo Kim
, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

A low power full accuracy MPEG1 Audio Layer 3(MP3) decoder with on-chip A/D Converter(ADC) and D/A Converter(DAC) is proposed. The chip is composed of a digital block to implement MP3 decoding algorithm and voice compression/decompression algorithm, a 12-bit recycling type ADC, and an oversampling Δ∑ 1-bit DAC. In order to satisfy the full accuracy specification of MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.3 um CMOS technology and the chip area is about 6.4×6.7 mm² with 165mW power dissipation at 2.7V power supply.

Original language	English
Pages (from-to)	903-906
Number of pages	4
Journal	IEEE Transactions on Consumer Electronics
Volume	46
Issue number	3
DOIs	https://doi.org/10.1109/30.883470
State	Published - Aug 2000

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10.1109/30.883470

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@article{07dde27605b84b54916c9fda4f4f497a,

title = "A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters",

abstract = "A low power full accuracy MPEG1 Audio Layer 3(MP3) decoder with on-chip A/D Converter(ADC) and D/A Converter(DAC) is proposed. The chip is composed of a digital block to implement MP3 decoding algorithm and voice compression/decompression algorithm, a 12-bit recycling type ADC, and an oversampling Δ∑ 1-bit DAC. In order to satisfy the full accuracy specification of MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.3 um CMOS technology and the chip area is about 6.4×6.7 mm2 with 165mW power dissipation at 2.7V power supply.",

author = "Sekyoung Hong and Dalsoo Kim and Minkyu Song",

year = "2000",

month = aug,

doi = "10.1109/30.883470",

language = "English",

volume = "46",

pages = "903--906",

journal = "IEEE Transactions on Consumer Electronics",

issn = "0098-3063",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

AU - Hong, Sekyoung

AU - Kim, Dalsoo

AU - Song, Minkyu

PY - 2000/8

Y1 - 2000/8

N2 - A low power full accuracy MPEG1 Audio Layer 3(MP3) decoder with on-chip A/D Converter(ADC) and D/A Converter(DAC) is proposed. The chip is composed of a digital block to implement MP3 decoding algorithm and voice compression/decompression algorithm, a 12-bit recycling type ADC, and an oversampling Δ∑ 1-bit DAC. In order to satisfy the full accuracy specification of MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.3 um CMOS technology and the chip area is about 6.4×6.7 mm2 with 165mW power dissipation at 2.7V power supply.

AB - A low power full accuracy MPEG1 Audio Layer 3(MP3) decoder with on-chip A/D Converter(ADC) and D/A Converter(DAC) is proposed. The chip is composed of a digital block to implement MP3 decoding algorithm and voice compression/decompression algorithm, a 12-bit recycling type ADC, and an oversampling Δ∑ 1-bit DAC. In order to satisfy the full accuracy specification of MP3 decoder, a novel 32-bit floating DSP core is proposed. Further, an efficient power management technique is implemented to reduce power consumption for portable applications. The proposed decoder has been fabricated with a 4 metal 0.3 um CMOS technology and the chip area is about 6.4×6.7 mm2 with 165mW power dissipation at 2.7V power supply.

UR - https://www.scopus.com/pages/publications/0034247369

U2 - 10.1109/30.883470

DO - 10.1109/30.883470

M3 - Article

AN - SCOPUS:0034247369

SN - 0098-3063

VL - 46

SP - 903

EP - 906

JO - IEEE Transactions on Consumer Electronics

JF - IEEE Transactions on Consumer Electronics

IS - 3

ER -

A low power full accuracy MPEG1 audio layer III (MP3) decoder with on-chip data converters

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