A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications

Jae Joon Kim, Chang Hyuk Cho, Kwan Yeob Chae, Sangjin Byun

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) with an integrating resolution booster (IRB) is proposed and experimentally verified to provide the capability of dual-mode operation, that is, low-power and high-resolution modes. This dual-mode architecture corresponds to a kind of hybrid ADC architecture, combining a low-power SAR ADC and a high-resolution integrating-type ADC together. A prototype ADC design is fabricated in a 0.18 μm CMOS process, and its dual-mode operation is experimentally verified. The total power consumption in the low-power mode was only 8 μW with the resolution of 6 bits, and the high-resolution mode achieved an additional resolution of 4 bits by activating the IRB, consuming the instant power of 380 μW.

Original languageEnglish
Pages (from-to)1730-1735
Number of pages6
JournalIEICE Electronics Express
Volume8
Issue number20
DOIs
StatePublished - 2011

Keywords

  • Dual-mode architecture
  • Integrating resolution booster
  • Successive approximation register
  • Wireless sensor

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