Abstract
A successive approximation register (SAR) analog-to-digital converter (ADC) with an integrating resolution booster (IRB) is proposed and experimentally verified to provide the capability of dual-mode operation, that is, low-power and high-resolution modes. This dual-mode architecture corresponds to a kind of hybrid ADC architecture, combining a low-power SAR ADC and a high-resolution integrating-type ADC together. A prototype ADC design is fabricated in a 0.18 μm CMOS process, and its dual-mode operation is experimentally verified. The total power consumption in the low-power mode was only 8 μW with the resolution of 6 bits, and the high-resolution mode achieved an additional resolution of 4 bits by activating the IRB, consuming the instant power of 380 μW.
Original language | English |
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Pages (from-to) | 1730-1735 |
Number of pages | 6 |
Journal | IEICE Electronics Express |
Volume | 8 |
Issue number | 20 |
DOIs | |
State | Published - 2011 |
Keywords
- Dual-mode architecture
- Integrating resolution booster
- Successive approximation register
- Wireless sensor