A multi-resolution mode CMOS image sensor with a novel two-step single-slope ADC for intelligent surveillance systems

Daehyeok Kim; Minkyu Song; Byeongseong Choe; Soo Youn Kim

doi:10.3390/s17071497

A multi-resolution mode CMOS image sensor with a novel two-step single-slope ADC for intelligent surveillance systems

Daehyeok Kim, Minkyu Song, Byeongseong Choe, Soo Youn Kim

Division of System Semiconductor

Dongguk University

Research output: Contribution to journal › Article › peer-review

17 Scopus citations

Abstract

In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 µm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 µm × 4.4 µm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.

Original language	English
Article number	1497
Journal	Sensors
Volume	17
Issue number	7
DOIs	https://doi.org/10.3390/s17071497
State	Published - Jul 2017

Keywords

CMOS image sensor
Fixed pattern noise
Intelligent surveillance system (ISS)
Low power consumption
Multi-mode pixel resolution
Two-step single-slope ADC

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10.3390/s17071497

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title = "A multi-resolution mode CMOS image sensor with a novel two-step single-slope ADC for intelligent surveillance systems",

abstract = "In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 µm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 µm × 4.4 µm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.",

keywords = "CMOS image sensor, Fixed pattern noise, Intelligent surveillance system (ISS), Low power consumption, Multi-mode pixel resolution, Two-step single-slope ADC",

author = "Daehyeok Kim and Minkyu Song and Byeongseong Choe and Kim, {Soo Youn}",

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AB - In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 µm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 µm × 4.4 µm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.

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KW - Fixed pattern noise

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KW - Low power consumption

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KW - Two-step single-slope ADC

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A multi-resolution mode CMOS image sensor with a novel two-step single-slope ADC for intelligent surveillance systems

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