A New CMOS Ultra Low Power Flip-Flop Circuit with a Minimization of Internal Node Transitions

Suhyenn Lee, Gyuwon Kam, Seungjoo Yoon, Soo Youn Kim, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, a new CMOS ultra low power flip-flop (ULPFF) circuit with a minimization technique of internal node transitions is discussed. In order to reduce power consumption, a new technique to eliminate short-circuit currents is also proposed. The proposed ULPFF is composed of 24 CMOS transistors, and it has the lowest power consumption among other conventional FFs.

Original languageEnglish
Title of host publicationITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages505-506
Number of pages2
ISBN (Electronic)9781665485593
DOIs
StatePublished - 2022
Event37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022 - Phuket, Thailand
Duration: 5 Jul 20228 Jul 2022

Publication series

NameITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications

Conference

Conference37th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2022
Country/TerritoryThailand
CityPhuket
Period5/07/228/07/22

Keywords

  • flip-flop circuit
  • internal node transitions
  • minimization technique
  • ultra low power

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