TY - GEN
T1 - A pixel-configurable CMOS image sensor for an intelligent surveillance system
AU - Yoo, Jieun
AU - Namgung, Seol
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/2/3
Y1 - 2016/2/3
N2 - A CMOS Image Sensor (CIS) mounted on a surveillance system does not always record a picture in a high resolution mode. In a normal state without any events or accidents, it is possible to take a picture in a low resolution mode to reduce power consumption. In this paper, a novel low power CIS which has two kinds of resolution mode is discussed to implement an intelligent surveillance system. Further, a pixel sub-sampling and a column shut-down technique are proposed. The prototype CIS chip is based on a 0.1μm CMOS process and satisfies a QVGA resolution (320×240) with a pitch of 5.0 μm and a 4-Tr active-pixel sensor structure. The fabricated CIS is composed of an analog correlated double sampling (CDS), an 8-bit single-slope ADC, and a digital counter. The operating speed of the CIS is 50 frame/s with a power consumption of 9.8mW at 2.8V(Analog)/1.5 V(Digital) power supply. When the pixel-configurable technique is used, the power consumption is about 2.7mW in a 1/4 low resolution mode. Therefore, the power consumption is drastically reduced, when the proposed technique is adopted.
AB - A CMOS Image Sensor (CIS) mounted on a surveillance system does not always record a picture in a high resolution mode. In a normal state without any events or accidents, it is possible to take a picture in a low resolution mode to reduce power consumption. In this paper, a novel low power CIS which has two kinds of resolution mode is discussed to implement an intelligent surveillance system. Further, a pixel sub-sampling and a column shut-down technique are proposed. The prototype CIS chip is based on a 0.1μm CMOS process and satisfies a QVGA resolution (320×240) with a pitch of 5.0 μm and a 4-Tr active-pixel sensor structure. The fabricated CIS is composed of an analog correlated double sampling (CDS), an 8-bit single-slope ADC, and a digital counter. The operating speed of the CIS is 50 frame/s with a power consumption of 9.8mW at 2.8V(Analog)/1.5 V(Digital) power supply. When the pixel-configurable technique is used, the power consumption is about 2.7mW in a 1/4 low resolution mode. Therefore, the power consumption is drastically reduced, when the proposed technique is adopted.
KW - analog correlated double sampling
KW - CMOS image sensor
KW - column shut-down technique
KW - intelligent surveillance system
KW - pixel configurable
KW - single-slope ADC
UR - http://www.scopus.com/inward/record.url?scp=84964969834&partnerID=8YFLogxK
U2 - 10.1109/GCCE.2015.7398522
DO - 10.1109/GCCE.2015.7398522
M3 - Conference contribution
AN - SCOPUS:84964969834
T3 - 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015
SP - 545
EP - 549
BT - 2015 IEEE 4th Global Conference on Consumer Electronics, GCCE 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th IEEE Global Conference on Consumer Electronics, GCCE 2015
Y2 - 27 October 2015 through 30 October 2015
ER -