A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18μm CMOS

Jeongsik Yang; Jinwook Kim; Sangjin Byun; Cormac Conroy; Beomsup Kim

A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18μm CMOS

Jeongsik Yang, Jinwook Kim, Sangjin Byun, Cormac Conroy, Beomsup Kim

Department of Electronics & Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

Abstract

A quad-channel serial-link transceiver provides 12.5Gb/s full duplex raw data rate for a single 10Gb XAUI interface. A mixed-mode IMS adaptive equalizer is adopted, which achieves 3dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64ps-pp jitter. The IC consumes 718mW at 3.125Gb/s/ch with full duplex data rate.

Original language	English
Pages (from-to)	134-135+489-490
Journal	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	47
State	Published - 2003
Event	Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement - San Francisco, CA., United States Duration: 15 Feb 2003 → 19 Feb 2003

Cite this

@article{15cd261ea96d4ac38426602995960edb,

title = "A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18μm CMOS",

abstract = "A quad-channel serial-link transceiver provides 12.5Gb/s full duplex raw data rate for a single 10Gb XAUI interface. A mixed-mode IMS adaptive equalizer is adopted, which achieves 3dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64ps-pp jitter. The IC consumes 718mW at 3.125Gb/s/ch with full duplex data rate.",

author = "Jeongsik Yang and Jinwook Kim and Sangjin Byun and Cormac Conroy and Beomsup Kim",

year = "2003",

language = "English",

volume = "47",

pages = "134--135+489--490",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement ; Conference date: 15-02-2003 Through 19-02-2003",

}

TY - JOUR

T1 - A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18μm CMOS

AU - Yang, Jeongsik

AU - Kim, Jinwook

AU - Byun, Sangjin

AU - Conroy, Cormac

AU - Kim, Beomsup

PY - 2003

Y1 - 2003

N2 - A quad-channel serial-link transceiver provides 12.5Gb/s full duplex raw data rate for a single 10Gb XAUI interface. A mixed-mode IMS adaptive equalizer is adopted, which achieves 3dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64ps-pp jitter. The IC consumes 718mW at 3.125Gb/s/ch with full duplex data rate.

AB - A quad-channel serial-link transceiver provides 12.5Gb/s full duplex raw data rate for a single 10Gb XAUI interface. A mixed-mode IMS adaptive equalizer is adopted, which achieves 3dB SNR improvement over pre-emphasis techniques. A delay-immune CDR circuit recovers the receive clock with 64ps-pp jitter. The IC consumes 718mW at 3.125Gb/s/ch with full duplex data rate.

UR - http://www.scopus.com/inward/record.url?scp=2442677952&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:2442677952

SN - 0193-6530

VL - 47

SP - 134-135+489-490

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement

Y2 - 15 February 2003 through 19 February 2003

ER -

A quad-channel 3.125Gb/s/ch serial-link transceiver with mixed-mode adaptive equalizer in 0.18μm CMOS

Abstract

Other files and links

Fingerprint

Cite this