TY - GEN
T1 - A small chip area 12-b 300MS/S Current Steering CMOS D/A converter based on a laminated-step layout technique
AU - Lee, Byungseung
AU - Kim, Byungill
AU - Lee, Juneseok
AU - Hwang, Sanghoon
AU - Song, Minkyu
AU - Wysocki, Tad
PY - 2007
Y1 - 2007
N2 - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.
AB - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.
UR - http://www.scopus.com/inward/record.url?scp=49749140705&partnerID=8YFLogxK
U2 - 10.1109/ECCTD.2007.4529738
DO - 10.1109/ECCTD.2007.4529738
M3 - Conference contribution
AN - SCOPUS:49749140705
SN - 1424413427
SN - 9781424413423
T3 - European Conference on Circuit Theory and Design 2007, ECCTD 2007
SP - 882
EP - 885
BT - European Conference on Circuit Theory and Design 2007, ECCTD 2007
PB - IEEE Computer Society
T2 - European Conference on Circuit Theory and Design 2007, ECCTD 2007
Y2 - 26 August 2007 through 30 August 2007
ER -