Address Translation Layer for Byte-Addressable Non-Volatile Memory-Based Solid State Drives

Because of the need for processing and managing the massive amounts of big data in smart/wearable devices and driverless vehicles, semiconductor companies are focusing on developing byte-addressable non-volatile memory (NVM)-based storage systems. The byte-addressable NVMs, such as phase-change memory, resistive memory, and magnetoresistive memory, are regarded as an alternative to NAND flash memories. There have been many proposals and studies on the use of NVM as main memory in the memory hierarchy. However, there has not been much academic research on using NVM as a substitute for NAND flash memories. This paper provides a system architecture for an NVM-based solid state drive based on some speculations/assumptions on the hardware characteristics of NVMs. It applies the previously proposed address-mapping algorithms of conventional solid state drives to the NVM-based solid state drives and examines their suitability. The optimization of I/O parallelism of static and dynamic address mapping algorithms is compared and analyzed. This paper also observes the effect of log block policies on the hardware characteristics of the NVMs.