An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder

Sunghyun Park; Jooho Hwang; Dongheon Lee; Junho Moon; Minkyu Song

doi:10.1109/NEWCAS.2009.5290477

An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder

Sunghyun Park, Jooho Hwang, Dongheon Lee, Junho Moon, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit IGSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascadedfolding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18pm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm² and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when F_in= F_s /2 at F_s=1GHz.

Original language	English
Title of host publication	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
DOIs	https://doi.org/10.1109/NEWCAS.2009.5290477
State	Published - 2009
Event	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 - Toulouse, France Duration: 28 Jun 2009 → 1 Jul 2009

Publication series

Name	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

Conference

Conference	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
Country/Territory	France
City	Toulouse
Period	28/06/09 → 1/07/09

Access to Document

10.1109/NEWCAS.2009.5290477

Cite this

Park, S., Hwang, J., Lee, D., Moon, J., & Song, M. (2009). An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 Article 5290477 (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09). https://doi.org/10.1109/NEWCAS.2009.5290477

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title = "An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder",

abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit IGSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascadedfolding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18pm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs /2 at Fs=1GHz.",

author = "Sunghyun Park and Jooho Hwang and Dongheon Lee and Junho Moon and Minkyu Song",

year = "2009",

doi = "10.1109/NEWCAS.2009.5290477",

language = "English",

isbn = "9781424445738",

series = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

booktitle = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

note = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 ; Conference date: 28-06-2009 Through 01-07-2009",

}

Park, S, Hwang, J, Lee, D, Moon, J & Song, M 2009, An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder. in 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09., 5290477, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, Toulouse, France, 28/06/09. https://doi.org/10.1109/NEWCAS.2009.5290477

An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder. / Park, Sunghyun; Hwang, Jooho; Lee, Dongheon et al.
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. 5290477 (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Park, Sunghyun

AU - Hwang, Jooho

AU - Lee, Dongheon

AU - Moon, Junho

AU - Song, Minkyu

PY - 2009

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N2 - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit IGSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascadedfolding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18pm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs /2 at Fs=1GHz.

AB - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit IGSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascadedfolding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18pm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply. The simulated result of SNDR is 46.29dB, when Fin= Fs /2 at Fs=1GHz.

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M3 - Conference contribution

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SN - 9781424445738

T3 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

BT - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

T2 - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

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Park S, Hwang J, Lee D, Moon J, Song M. An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. 5290477. (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09). doi: 10.1109/NEWCAS.2009.5290477

An 8-bit IGSPS folding-interpolation CMOS A/D converter with an auto switching encoder

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