An enhanced dynamic-range CMOS image sensor using a digital logarithmic single-slope ADC

Daeyun Kim, Minkyu Song

Research output: Contribution to journalArticlepeer-review

29 Scopus citations

Abstract

Many kinds of wide-dynamic-range (DR) CMOS image sensors (CIS) have been developed, such as a multiple sampling, a multiple exposure technique, etc. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this brief, a new digital logarithmic single-slope analog-to-digital converter (SS-ADC) with a digital counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic SS-ADC enhances the DR by 24 dB. The proposed ADC, which has been fabricated using a 0.13-μ m CIS process, achieves a signal-to-noise- plus-distortion ratio of 57.6 dB at 50 kS/s.

Original languageEnglish
Article number6290348
Pages (from-to)653-657
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume59
Issue number10
DOIs
StatePublished - 2012

Keywords

  • CMOS image sensor (CIS)
  • logarithmic analog-to-digital converter (ADC)
  • single-slope ADC (SS-ADC)
  • wide dynamic range (WDR)

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