An implementation of low latency address-mapping logic for SSD controllers

Yuchan Song, Hyunjoo So, Yongjae Chun, Hyun Seok Kim, Youpyo Hong

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.

Original languageEnglish
Article number20190521
Pages (from-to)1-6
Number of pages6
JournalIEICE Electronics Express
Volume16
Issue number21
DOIs
StatePublished - 2019

Keywords

  • FTL
  • SSD

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