An implementation of low latency address-mapping logic for SSD controllers

Yuchan Song; Hyunjoo So; Yongjae Chun; Hyun Seok Kim; Youpyo Hong

doi:10.1587/elex.16.20190521

An implementation of low latency address-mapping logic for SSD controllers

Yuchan Song
, Hyunjoo So
, Yongjae Chun
, Hyun Seok Kim
, Youpyo Hong

Department of Electronics & Electrical Engineering

Dongguk University

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.

Original language	English
Article number	20190521
Pages (from-to)	1-6
Number of pages	6
Journal	IEICE Electronics Express
Volume	16
Issue number	21
DOIs	https://doi.org/10.1587/elex.16.20190521
State	Published - 2019

Keywords

FTL
SSD

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10.1587/elex.16.20190521

Cite this

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title = "An implementation of low latency address-mapping logic for SSD controllers",

abstract = "Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.",

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AU - Hong, Youpyo

PY - 2019

Y1 - 2019

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AB - Solid-state drives (SSDs) are replacing hard-disk drives (HDDs) because of their advantages of light weight, low power, and high speed. A flash translation layer (FTL) is a key to achieving a high efficiency in accessing an SSD. This letter presents an architecture to implement the mapping between the logical address and the physical address as hardwired to reduce the workload of the FTL inside an SSD.

KW - FTL

KW - SSD

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DO - 10.1587/elex.16.20190521

M3 - Article

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An implementation of low latency address-mapping logic for SSD controllers

Abstract

Keywords

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