An interpolated flash type 6-b CMOS A/D converter with a DC reference fluctuation reduction technique

Yujin Park, Sanghoon Hwang, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with a 6-bit 2GSPS at 1.8V is described. The architecture of the proposed ADC is based on a flash type ADC with interpolation technique to obtain a high-speed operation. In order to overcome the problems of high speed operation, a circuit to reduce the reference fluctuation, a resistor-based offset averaging technique, and a novel One-Zero detecting encoder are proposed. The fabricated chip with 0.18um CMOS occupies an area of 977um × 1040um and consumes 145mW at 1.8V power supply. The measured DNL is within 0.5LSB, and the measured SNDR is about 34.55dB, when the input frequency is 10MHz at 2GHz sampling frequency.

Original languageEnglish
Title of host publicationProceedings of the 2005 European Conference on Circuit Theory and Design
Pages123-126
Number of pages4
DOIs
StatePublished - 2005
Event2005 European Conference on Circuit Theory and Design - Cork, Ireland
Duration: 28 Aug 20052 Sep 2005

Publication series

NameProceedings of the 2005 European Conference on Circuit Theory and Design
Volume1

Conference

Conference2005 European Conference on Circuit Theory and Design
Country/TerritoryIreland
CityCork
Period28/08/052/09/05

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