Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors

This paper presents an analysis and design of an 884-MHz, −41.8-dBm input power sensitivity, 570-stage CMOS RF-DC rectifier with ground shielded input coupling capacitors. First, we have presented the input impedance model of an N-stage CMOS RF-DC rectifier by applying 1-Y transform to the input coupling capacitors and including a nonlinear input resistance of the MOS transistors. Based on the developed model, we have carried out the steady-state and transient analyses of the N-stage RF-DC rectifier. According to the analysis results, the input power sensitivity increases as the RF-DC rectifier contains more rectifier cells. However, integrating a large number of rectifier cells normally reduces the passive amplification gain of the matching network and thus may not bring the desired results. In this paper, we propose the RF-DC rectifier adopting a metal ground shield plane beneath the input coupling capacitors thereby incorporating as many as 570 rectifier cells without lowering the passive amplification gain. By doing so, the 884-MHz, 570-stage RF-DC rectifier implemented in a 28nm CMOS process achieves the measured input power sensitivity of −41.8dBm at 1V output DC voltage. The measured recharging time from 0.88V to 1.0V is 11.1 seconds when the storage capacitor is 1nF.