Abstract
This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the two-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.
Original language | English |
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Pages | 256-261 |
Number of pages | 6 |
DOIs | |
State | Published - 2000 |
Event | International Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy Duration: 26 Jul 2000 → 27 Jul 2000 |
Conference
Conference | International Symposium on low Power Electronics and Design (ISLPED'2000) |
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City | Portacino Coast, Italy |
Period | 26/07/00 → 27/07/00 |