Asynchronous matrix-vector multiplier for discrete cosine transform

Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

This paper proposes an efficient asynchronous hardwired matrix-vector multiplier for the two-dimensional discrete cosine transform and inverse discrete cosine transform (DCT/IDCT). The design achieves low power and high performance by taking advantage of the typically large fraction of zero and small-valued data in DCT and IDCT applications. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit-partitioned adders using simplified, static-logic-based speculative completion sensing. The results extracted by both bit-level analysis and HSPICE simulations indicate significant improvements compared to traditional designs.

Original languageEnglish
Pages256-261
Number of pages6
DOIs
StatePublished - 2000
EventInternational Symposium on low Power Electronics and Design (ISLPED'2000) - Portacino Coast, Italy
Duration: 26 Jul 200027 Jul 2000

Conference

ConferenceInternational Symposium on low Power Electronics and Design (ISLPED'2000)
CityPortacino Coast, Italy
Period26/07/0027/07/00

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