Bus encoding for low-power high-performance memory systems

Naehyuck Chang, Kwanho Kim, Jinsung Cho

Research output: Contribution to journalConference articlepeer-review

31 Scopus citations

Abstract

High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL_2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace data-driven simulations. We had reduction of 14% with random data and up to 67.5% with trace data.

Original languageEnglish
Pages (from-to)800-805
Number of pages6
JournalProceedings - Design Automation Conference
DOIs
StatePublished - 2000
EventDAC 2000: 37th Design Automation Conference - Los Angeles, CA, USA
Duration: 5 Jun 20009 Jun 2000

Fingerprint

Dive into the research topics of 'Bus encoding for low-power high-performance memory systems'. Together they form a unique fingerprint.

Cite this