@inproceedings{9a3dce3fdf9749808e9c8b3cb1c3dd09,
title = "Column-selection-enabled 8T SRAM array with 1R/1W multi-port operation for DVFS-enabled processors",
abstract = "In this work, we propose a new multi-port 8T SRAM architecture suitable for DVFS enabled processors. With multi-way caches using 8T SRAM, write-back operations are required to support column selection. While conventional write-back schemes may not have the 1R/1W dual port advantage of 8T SRAM, our proposed local write-back scheme preserves both ports with only minimal limitations. Simulation results show significant IPC enhancements with the proposed cache. Implementation in 45nm technology demonstrates wide-range DVFS (from
[email protected] to 710MHz@1V) for the proposed SRAM array.",
keywords = "8T SRAM, Cache Memory, DVFS, Low-Power",
author = "Park, {Sang Phill} and Kim, {Soo Youn} and Dongsoo Lee and Kim, {Jae Joon} and Griffin, {W. Paul} and Kaushik Roy",
year = "2011",
doi = "10.1109/ISLPED.2011.5993654",
language = "English",
isbn = "9781612846590",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
pages = "303--308",
booktitle = "IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011",
note = "17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 ; Conference date: 01-08-2011 Through 03-08-2011",
}