@inproceedings{9d9305bd8e624020b3a116cf549fb6c0,
title = "Compute-in-Memory with SAR ADC and 2T1C DRAM for MAC Operations",
abstract = "This paper presents a compute-in-memory (CIM) architecture for MAC operation using 2T1 C dynamic random access memory (DRAM) and a successive-approximation analog-to-digital converter (SAR ADC). The proposed design features CIM analog multiplication and summation architecture consisting of a digital-to-time converter (DTC) and SAR ADC. The DTC converts the input code into clock-based pulse width, and the calculation can be done by passing through pulse into a 2T1C DRAM array in parallel. The proposed structure is implemented using a 28-nm CMOS process, operates four parallel 2-bit× 4-bit multiplication and total summation simultaneously, and a single calculation requires 140ns for 100MHz system clock frequency.",
keywords = "2T1C DRAM, Compute-In-Memory, Process-In-Memory, Successive approximation analog-to-digital converter",
author = "Jang, {Tae Eun} and Lee, {Kyu Hyun} and Kim, {Gi Yeol} and Yun, {Su Yeon} and Youn, {Da Hyeon} and Hyunggu Choi and Jihyang Kim and Kim, {Soo Youn} and Minkyu Song",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 ; Conference date: 28-01-2024 Through 31-01-2024",
year = "2024",
doi = "10.1109/ICEIC61013.2024.10457128",
language = "English",
series = "2024 International Conference on Electronics, Information, and Communication, ICEIC 2024",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 International Conference on Electronics, Information, and Communication, ICEIC 2024",
address = "United States",
}