Crystallization-Induced Interface Control in Poly-Si Flash for High-Accuracy Neuromorphic Inference

This paper presents a comprehensive analysis of the impact of polycrystalline silicon (poly-Si) channel formation methods on the electrical characteristics of charge-trap flash (CTF) memory, with particular attention to their suitability for synaptic applications in neuromorphic systems. T wo types of poly-Si formation methods, low-pressure chemical vapor deposition (LPCVD) and solid-phase crystallization (SPC), were experimentally evaluated and compared. First, the surface roughness of SPC poly-Si was verified to be 9.39× lower than that of LPCVD poly-Si, effectively reducing local electric field concentration. This mitigates read disturbance and overprogramming effects, consequently enabling 2.29× more reliable conductance states. Second, a smaller grain size was confirmed in LPCVD poly-Si, contributing to reduced power consumption. However, the rough surface morphology of LPCVD poly-Si significantly limits its applicability in reliable analog operations. Therefore, the grain size of SPC poly-Si was further optimized by adjusting the annealing conditions, aiming to achieve low-power operation while maintaining superior analogue performance and reliability. As a result, it was confirmed that lower annealing temperatures resulted in smaller grain sizes, leading to a 60% reduction in drive current. Finally, CNN-based image classification on the CIFAR-10 data set demonstrated a 3.98%