Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter

Changsun Baek, Chaeyeol Lim, Daeyun Kim, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Scopus citations

Abstract

In this paper, a 320×240 pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain a 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column counter type, and the frame rate is approximately 40% faster than the double memories type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung 0.13μm 1P4M CMOS process and used a 4T APS with a pixel pitch of 2.25μm. The measured column fixed pattern noise (FPN) is 0.10 LSB.

Original languageEnglish
Title of host publication2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages393-397
Number of pages5
DOIs
StatePublished - 2012
Event38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France
Duration: 17 Sep 201221 Sep 2012

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Conference

Conference38th European Solid State Circuits Conference, ESSCIRC 2012
Country/TerritoryFrance
CityBordeaux
Period17/09/1221/09/12

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