TY - GEN
T1 - Design of a 1.8V 10bit 300MSPS CMOS digital-to-analog converter with a novel deglitching circuit and inverse thermometer decoder
AU - Yoo, Yongsang
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - In this paper, a 1.8 V 10 bit 300 MSPS CMOS digital-to-analog converter (DAC) is described. The architecture of the D/A converter is based on a current steering 8+2 segmented type, which reduces non-linearity errors and other secondary effects. In order to achieve a high performance D/A converter, a novel current cell with a low spurious deglitching circuit and a novel row/column 4 to 15 inverse thermometer decoder are proposed. To verify the performance, the device is integrated with 0.25 μm CMOS 1-poly 5-metal technology. The effective chip area is 1.56 mm2 and power consumption is about 84 mW at 2.5 V power supply. The simulation and experimental results show that the glitch energy is 0.9 pV·sec at fs=100 MHz, 15 pV·sec at fs=300 MHz in worst case, respectively. Furthermore, both INL and DNL are within ±1.0 LSB, and the SFDR is about 59 dB when the sampling frequency is 300 MHz and output frequency is 3 MHz.
AB - In this paper, a 1.8 V 10 bit 300 MSPS CMOS digital-to-analog converter (DAC) is described. The architecture of the D/A converter is based on a current steering 8+2 segmented type, which reduces non-linearity errors and other secondary effects. In order to achieve a high performance D/A converter, a novel current cell with a low spurious deglitching circuit and a novel row/column 4 to 15 inverse thermometer decoder are proposed. To verify the performance, the device is integrated with 0.25 μm CMOS 1-poly 5-metal technology. The effective chip area is 1.56 mm2 and power consumption is about 84 mW at 2.5 V power supply. The simulation and experimental results show that the glitch energy is 0.9 pV·sec at fs=100 MHz, 15 pV·sec at fs=300 MHz in worst case, respectively. Furthermore, both INL and DNL are within ±1.0 LSB, and the SFDR is about 59 dB when the sampling frequency is 300 MHz and output frequency is 3 MHz.
KW - Analog-digital conversion
KW - CMOS analog integrated circuits
KW - CMOS digital integrated circuits
KW - CMOS technology
KW - Decoding
KW - Digital-analog conversion
KW - Graphics
KW - Semiconductor device noise
KW - Voltage control
KW - Voltage fluctuations
UR - http://www.scopus.com/inward/record.url?scp=84936932986&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2002.1115245
DO - 10.1109/APCCAS.2002.1115245
M3 - Conference contribution
AN - SCOPUS:84936932986
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 311
EP - 314
BT - Proceedings - APCCAS 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Y2 - 28 October 2002 through 31 October 2002
ER -